I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a synchronous, multi- master, multi-slave, packet switched, single-ended, serial computer bus invented in by Philips Semiconductor (now NXP Semiconductors). Alternatively I²C is spelled I2C (pronounced I-two-C) or IIC (pronounced I-I-C). Since October Industry Standard. The “I2C Bus Specification,” published by Philips Semiconductor, provides a communication protocol definition of the signal activity on the I2C. I2C specification defines the interface, signals, addressing, protocols and electrical The I2C bus uses two wires: serial data (SDA) and serial clock (SCL). . A complete I2C Bus Specification and User Manual can be obtained from the NXP.

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After every philips i2c protocol data bits in one direction, an “acknowledge” bit is transmitted in the other direction. Some slave devices have few bits of the I2C address dependent on the level of address pins.

I²C – Wikipedia

High-speed mode introduces also few differences or improvements in the specifications: That is another incompatibility with SMBus: This is in contrast to the start bits and stop bits used philips i2c protocol asynchronous serial communicationwhich are distinguished from data bits only by their timing.

Clock Synchronization and Handshaking Slave devices that need some time to process received byte or are not ready yet to send the next byte, can pull the clock low to signal to the master that it should wait. Interfaces are listed by their speed in the roughly ascending order, so the interface at the end of each section philips i2c protocol be the fastest.

Technical and de facto standards for wired computer buses. Many complex embedded boards contain a large number of different I2C devices. Philips i2c protocol combination holds the SDA line low for 7 clock pulses and allows simple detection of active I2C bus with lower sampling frequency.

High-speed systems and some others may use a current source instead of a resistor to pull-up on SCL or both SCL and SDA, to accommodate higher bus capacitance and enable faster rise times. Philips i2c protocol from ” https: The master then waits for SCL to actually go high; this will be delayed by the finite rise time of the SCL signal the RC time constant of the pull-up resistor and the parasitic capacitance of the bus and may be philips i2c protocol delayed by a slave’s clock stretching.


The general call address is used to address all devices on the slave bus.

The terminating STOP indicates when those grouped actions should take effect. However, if the I2C philips i2c protocol is implemented by the software, the microcontroller has to sample SDA line at least twice per clock pulse in order to detect changes.

One purpose of SMBus is to promote robustness and interoperability. The most common form of the latter is a write message providing intra-device address philips i2c protocol, followed by a read message.

All devices on the bus must have open-collector or open-drain pins. In other projects Wikimedia Commons.

Access Denied

In particular, is reserved for the SMBus host, which may be used by master-capable devices, is the “SMBus alert phiilps address” which is polled by the host after an out-of-band interrupt, and is the default address which is initially used by devices capable of dynamic address assignment. Slave This is the device that listens to the bus and is addressed protool the master.

Otherwise, if the data direction bit is 1, the master will read from slave device. Note the bit rates ;rotocol quoted for the transfers between master and slave without clock stretching or other hardware overhead. Since the two masters may send messages to the same slave address, and addresses philips i2c protocol refer to multiple slaves, arbitration must continue philips i2c protocol the data stages.

I2C Bus Specification

Hosts supporting the phhilips speeds are rare. Not all of them require proprietary drivers or APIs. The I2C bus uses two wires: Each slave device on the bus should have a phiilips 7-bit address. Synchronization Each master must generate its own clock signal and the data can change only when the clock is low. For this reason, when a slave can be accessed by multiple masters, philips i2c protocol command recognized by the slave either must be idempotent or must philips i2c protocol guaranteed never to be issued by two masters at the same time.


The number of the devices on a single prtocol is almost unlimited — philips i2c protocol only requirement is that the bus capacitance does not exceed pF. Archived from the original on Start Byte If microcontroller has I2C hardware and the microcontroller acts as a slave then the software needs to do nothing to check the bus state.

A transaction consisting of a single message is called either a read or a write transaction. If the master needs to communicate philips i2c protocol other slaves it can generate a repeated start with another slave address philipz generation Stop condition.

Fast mode devices are downward-compatible and can work with slower I2C controllers. Thus the actual transfer rate of user data is lower than those peak bit rates alone would imply. Thus it is common for designs to include a reset signal that provides an external method philips i2c protocol resetting the bus devices. Analog switches maintain the bidirectional nature of the lines philips i2c protocol do not isolate the capacitance of one segment from another or provide buffering capability.

Sometimes the master needs to write some data and then read from the slave device.

Specification – I2C Bus

Data on the I2C bus is transferred in 8-bit packets bytes. The transmitter and receiver switch roles philips i2c protocol one bit, and the original receiver transmits a single “0” bit ACK back. Those bytes determine how subsequent written bytes are treated or how the slave responds on subsequent reads.